1. Field of the Invention
The present invention relates generally to a semiconductor protecting apparatus and, more particularly to a semiconductor protecting apparatus and a method for preventing destruction of a semiconductor device caused by latch-up.
2. Description of the Background Art
In a semiconductor integrated circuit device of a CMOS structure, N type regions and P type regions forming elements of transistors and the like which are to be originally incorporated therein equivalently forms elements other than these elements. The elements formed equivalently are so-called parasitic thyristor element parasitizing the original elements.
It is known that a phenomenon called latch-up allowing large current to flow between power supply terminals is caused by operation of such parasitic thyristor elements in a conventional semiconductor integrated circuit device. Referring to FIG. 5, latch-up will be briefly described.
FIG. 5 is a diagram showing an example of a sectional structure of a semiconductor integrated circuit device of a CMOS structure.
A P type substrate 100 having a low impurity concentration comprises a region where an N channel MOS transistor is formed and a region where a P channel MOS transistor is formed on a main surface.
The N channel MOS transistor comprises N type regions 700 and 800 formed on P type substrate 100 as a drain and a source, respectively, and a gate electrode 900 formed above the substrate 100 with an insulating film interposed and between N type regions 700 and 800.
The P channel MOS transistor is formed in an N well 200 formed on P type substrate 100. The P channel MOS transistor comprises P type regions 400 and 500 formed on an N well 200 as a source and a drain, respectively, and a gate electrode 600 formed above the substrate 100 with an insulating film interposed and between p type regions 400 and 500 on N well 200.
On N well 200, an N type region 300 having an N type impurity concentration higher than that of N well 200 is formed in order to apply a back gate voltage to the P channel MOS transistor.
Similarly, on P type substrate 100, a P type region 150 having a P type impurity concentration higher than that of P type substrate 100 is formed in order to apply the back gate voltage to the N channel MOS transistor.
Power supply voltage Vcc is applied to N type region 300 and P type region 400. A ground potential Vss is applied to N type region 800 and P type region 150.
When the potential of N type region 700 falls below ground potential Vss, a PN junction formed of N type region 700 and P type substrate 100 is brought into a forward biased state and electrons flow out of N type region 700 into P type substrate 100. These electrons flow into N well 200 having a high potential and reach N type region 300. That is, a current flows from N type region 300 to N type region 700 through N well 200 and P type substrate 100.
When a PN junction formed of P type region 400 and N well 200 is brought into a forward biased state by a voltage drop caused in N well 200 by the current, holes flow out of P type region 400 into N well 200. These holes flow out of N well 200 to N type region 800 having a low potential through P type substrate 100. That is, a current flows from P type region 400 to N type region 800 through N well 200 and P type substrate 100.
The current increases a forward voltage, which is applied to the PN junction formed of N type region 700 and P type substrate 100, so that more electrons flow out N type region 700 into P type substrate 100. Therefore, as long as power supply voltage Vcc and ground potential Vss are applied to P type region 400 and N type region 300, and N type region 800 and P type region 150, respectively, more current flows from P type region 400 to N type region 800 through N well 200 and P type substrate 100 according to the above-mentioned mechanism.
P type region 400 is connected to power supply pad 250 receiving external power supply voltage Vcc through an interconnection 350 formed of metal such as aluminum. N type region 800 is connected to a ground pad 450 receiving external ground potential Vss through an interconnection 550 formed of metal such as aluminum.
In practice, interconnections 350 and 550, and power supply pad 250 and ground pad 450 are provided in the periphery of P type substrate 100 in order to supply the external power supply voltage to circuitry formed on P type substrate 100.
In order to prevent latch-up, a method has been used in which the potential of P type substrate 100 is kept lower than ground potential Vss by applying a negative voltage to P type substrate 100. This voltage with which the substrate is biased in order to prevent latch-up is termed a substrate bias voltage V.sub.BB . The substrate bias voltage V.sub.BB is applied to the substrate through an impurity region formed on the substrate and having the same conductivity type as the substrate.
Such a substrate bias voltage V.sub.BB is generally generated within a semiconductor integrated circuit device. Because of that, a conventional semiconductor integrated circuit device is provided with a substrate bias voltage generating circuit 12 for generating substrate bias voltage V.sub.BB formed on the same semiconductor substrate as the other circuit portions are formed.
However, even applying such a substrate bias voltage can not prevent latch-up completely.
As described above, in a conventional semiconductor integrated circuit device, a circuit formed on a semiconductor substrate is directly connected to a power supply pad and a ground pad receiving an external power supply voltage for driving the circuit through an interconnection of metal such as aluminum. Hence, once latch-up is caused as described above, the latch-up state is maintained unless the external power supply continues to be applied to the device.
For example, referring to FIG. 5, when a power is supplied externally, current is constantly supplied to p type region 400 from power supply pad 250 and current is constantly drawn out from N type region 800 to ground pad 450, so that the potential of N type region 700 is below ground potential Vss. Consequently, as described above, once current starts to flow from P type region 400 to N type region 800 through N well 200 and P type substrate 100, the current keeps flowing from power supply pad 250 to ground pad 450 through interconnection 350, P type region 400, N well 200, P type substrate 100, N type region 800, and interconnection 550.
If such large current keeps flowing in a semiconductor integrated device, then the semiconductor integrated circuit chip is heated by the current and eventually the whole circuit formed on the chip is destroyed.